Phase-locked loop (PLL) and delay-locked loop (DLL) integrated circuits are frequently used to generate highly accurate internal clock signals on integrated circuit substrates (e.g., chips). However, such conventional PLL and DLL integrated circuits are frequently susceptible to unwanted clock skew and jitter as clock speed and circuit integration levels are increased. In particular, PLLs typically suffer from phase error accumulation that may persist for long periods of time in noisy environments, whereas DLLs may have lower jitter performance because phase error accumulation does not occur. Thus, DLLs may offer an important alternative to PLLs in cases where a reference clock signal comes from a low-jitter source. However, DLLs typically cannot be used in applications where frequency tracking is required, such as frequency synthesis and clock recovery. DLLs may also be difficult to design for environments that experience significant process, voltage and temperature (PVT) variations.
The operating frequency range of conventional DLLs is also frequently limited because DLLs adjust only phase and not frequency. For example, the conventional DLL 10 of FIG. 1 may be limited to a relatively narrow frequency range of operation. As illustrated, the DLL 10 includes a voltage-controlled delay line (VCDL) 12, which generates an output clock signal DLLCLK in response to a reference clock signal REFCLK, a phase detector (PD) 14, charge pump (CP) 16 and a loop filter (LF) 18 that generates an analog control voltage VC. This control voltage VC is provided as a bias signal to a plurality of identical delay elements 15. When the delay time (TVCDL) of the VCDL 12 is initially shorter (or longer) than the period (TCLK) of the reference clock signal REFCLK, the DLL 10 automatically adjusts the delay time TVCDL until a phase difference between the reference clock signal REFCLK and the output clock signal DLLCLK is eliminated. This phase difference is detected by sampling the reference clock signal REFCLK with the rising edges of the output clock signal DLLCLK, which is provided as a feedback clock signal. This sampling is performed by the phase detector 14, which generates UP or DOWN pulses that are provided to the charge pump 16. These pulses charge (or discharge) a capacitor in the loop filter 18, thereby decreasing (or increasing) the control voltage VC and gradually reducing the phase difference by adjusting the delay of the delay elements 15.
Unfortunately, the performance of the DLL 10 of FIG. 1 may be limited by a stuck or harmonic lock problem. To avoid this problem, the minimum delay time (TVCDL-min) of the VCDL 12 should be located between ½TCLK and TCLK and the maximum delay time (TVCDL-min) of the VCDL 12 should be located between TCLK and 1.5TCLK. These relationships result in a maximum range of TCLK as follows: 0.677(TVCDL-max)<TCLK<TVCDL-max, where TVCDL-max=2TVCDL-min. However, if TVCDL-max≧3TVCDL-min, there is no range of TCLK that meets these conditions and the DLL 10 becomes prone to the stuck problem. Because the PVT variations associated with the delay time TVCDL can be as much as 2:1 in a typical CMOS process, the stuck-free condition can be satisfied over only a very narrow range of TCLK when the DLL 10 of FIG. 1 is used.
To address these problems associated with conventional DLLs, analog DLLs that utilize replica delay lines have been proposed. For example, FIG. 2 illustrates an analog DLL 20 having a main delay line (within a core DLL) and a replica delay line (RDL) 26 therein. The main delay line includes a plurality of delay elements 25 that generate an output clock signal DLLCLK. This output clock signal DLLCLK is provided as a feedback clock signal to a phase detector 14′, which also receives a reference clock signal REFCLK. The core DLL also includes a charge pump 16′ and a loop filter 18′, which generates a fine-tune control voltage Vcp. The delay provided by the main delay line is controlled primarily by a control voltage Vcr that is generated by the replica delay line 26. The replica delay line 26 consists of a single replica delay cell 25′, a current steering phase detector (CSPD) 22 and a low-pass filed (LPF) 24. Because of a sharing of the control voltage Vcr, the delay time of the replica delay cell 25′ is almost equal to the delay time of each of the delay elements 25 in the main delay line. The delay time of the replica delay cell 25′ will equal the delay time of each of the delay elements 25 in the main delay line if the fine-tune control voltage Vcp equals the bias voltage BIAS. If the current steering phase detector 22 is designed appropriately, the delay time of the replica delay cell 25′ can be made to equal one-eighth the period (TCLK) of the reference clock signal REFCLK. Accordingly, the delay provided by the main delay line will equal TCLK when the number of delay elements 25 in the main delay line equals eight. In this manner, the wide frequency range of the replica delay line 26 will translate to a core DLL having well established operating frequency bounds and generally stuck-free operation. The DLL 20 of FIG. 2 is more fully described in an article by Y. Moon et al, entitled “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,” IEEE Journal of Solid State Electronics, Vol. 25, No. 3, pp. 377-384, March 2000. Unfortunately, this DLL 20 will typically not lock when the minimum delay of the main delay line plus any fixed delay in the main feedback path is greater than the clock period. Moreover, the use of a replica delay line requires the use of an additional charge pump, which can significantly increase the area and power consumption requirements of the DLL.
Thus, notwithstanding these conventional DLLs, therein continues to be a need for alternative DLLs having stuck-free operation and high degrees of jitter immunity.